1. Field of the Invention
The invention relates to a protection device, a complementary protection device, a signal output device, a latch-up preventing method, and a computer-readable medium in which a program is stored, and particularly to a protection device, a complementary protection device, a signal output device, and a latch-up preventing method for preventing latch-up of a switching element of a protection target, and a computer-readable medium in which a program is stored.
2. Description of the Related Art
Conventionally, for example, if an overcurrent is output from an output stage of an amplifier that is used while connected to a speaker, the overcurrent is detected by an overcurrent detecting circuit to output a detecting signal to a control circuit, and the amplifier is powered down to prevent a switching element (the protection-target switching element) constituting the output stage from being broken down by the overcurrent (for example, see Japanese Patent Application Laid-Open No. 2005-252494 and No. 03-159408). As used herein, the “power-down” means that an output from the amplifier is stopped, and specifically that driving of the switching element of the protection target is stopped. Hereinafter, a time when the overcurrent is not generated is referred to as a “normal time”.
FIG. 9 illustrates an example of an amplifier 100 of the related art that can be powered down. As illustrated in FIG. 9, the amplifier 100 includes a differential stage 102, an offset stage 104, and an output stage 105. The output stage 105 includes P-channel type MOS field effect transistors (hereinafter referred to as “PMOS transistors”) 106 and 108, N-channel type MOS field effect transistors (hereinafter referred to as “NMOS transistors”) 110 and 112, and an output terminal 114. One end of a coil 116 is connected to the output terminal 114. The other end of the coil 116 is grounded. At this point, by way of example, the coil 116 having an inductor component of 500 nH is connected to the output terminal 114.
The differential stage 102 includes a positive input terminal 102A to which a positive input signal is input, a negative input terminal 102B to which a negative input signal is input, a power supply terminal 102C that is connected to a power supply wire VDD through which a driving positive electrode voltage is provided to the amplifier 100, and a ground terminal 102D that is connected to a ground wire GND through which a ground voltage is provided to the amplifier 100. The differential stage 102 amplifies a difference voltage signal indicating a difference voltage between the positive input signal input to the positive input terminal 102A and the negative input signal input to the negative input terminal 102B and outputs the amplified difference voltage signal to the subsequent offset stage 104.
The offset stage 104 is connected to the differential stage 102 such that the difference voltage signal is input to the offset stage 104, and the offset stage 104 generates and outputs a differential voltage in which an offset voltage component generated in the differential stage 102 is removed from the difference voltage signal. The offset stage 104 includes an output terminal 104A that is an output terminal in a negative output state at the normal time and outputs a positive-electrode differential signal obtained by removing the offset voltage component from the input difference voltage signal, an output terminal 104B that is an output terminal in a positive output state at the normal time and outputs a negative-electrode differential signal obtained by removing the offset voltage component from the input difference voltage signal, a power supply terminal 104C that is connected to the power supply wire VDD, and a ground terminal 104D that is connected to the ground wire GND.
The PMOS transistor 106 is a target (the protection-target switching element) to be protected from a latch-up. The PMOS transistor 106 includes a gate terminal that is connected to the output terminal 104A, a source terminal that is connected to power supply wire VDD, and a drain terminal that is connected to the output terminal 114. The PMOS transistor 106 is configured such that a conduction state at the normal time becomes a non-conduction state between the source terminal and the drain terminal when an off-voltage (a voltage at which the non-conduction state is established between the source terminal and the drain terminal) is applied to the gate terminal.
The PMOS transistor 108 is a switching element that establishes the non-conduction state between the source terminal and the drain terminal of the PMOS transistor 106 when an overcurrent detecting circuit (not illustrated) detects the overcurrent in the amplifier 100. The PMOS transistor 108 includes a source terminal that is connected to the power supply wire VDD, a drain terminal that is connected to the gate terminal of the PMOS transistor 106, and a gate terminal. The gate terminal of the PMOS transistor 108 is connected to a control circuit (not illustrated) connected to the overcurrent detecting circuit, and the off-voltage is applied to the gate terminal at the normal time by the control circuit.
The NMOS transistor 110 is a second protection-target switching element, and includes a gate terminal that is connected to the output terminal 104B, a source terminal that is connected to the ground wire GND, and a drain terminal that is connected to the output terminal 114. The NMOS transistor 110 is configured such that the conduction state at the normal time becomes the non-conduction state between the source terminal and the drain terminal when the off-voltage is applied to the gate terminal.
The NMOS transistor 112 establishes the non-conduction state between the source terminal and the drain terminal of the NMOS transistor 110 when the overcurrent detecting circuit detects the overcurrent in the amplifier 100. The NMOS transistor 112 includes a source terminal that is connected to the power supply wire VDD, a drain terminal that is connected to the gate terminal of the NMOS transistor 110, and a gate terminal. The gate terminal of the NMOS transistor 112 is connected to the control circuit, and the off-voltage is applied to the gate terminal at the normal time by the control circuit.
In the amplifier 100 having the above-described configuration, when the overcurrent detecting circuit detects the overcurrent, the control circuit controls the PMOS transistor 108 and the NMOS transistor 112 such that the non-conduction state is established between the source terminal and the drain terminal of each of the PMOS transistor 106 and the NMOS transistor 110. That is, the voltage applied to the gate terminal of each of the PMOS transistor 108 and the NMOS transistor 112 is controlled such that the conduction state is established between the source terminal and the drain terminal of each of the PMOS transistor 108 and the NMOS transistor 112. Therefore, the off-voltage is applied to the gate terminal of each of the PMOS transistor 108 and the NMOS transistor 110 to cut off the overcurrent.
Because the off-voltage is rapidly applied to the gate terminal of each of the PMOS transistor 106 and the NMOS transistor 110 (for an example of the change with time of the voltage applied to the gate terminal of the PMOS transistor 106, see FIG. 10B), the conduction state is rapidly changed to the non-conduction state between the source terminal and the drain terminal of each of the PMOS transistor 106 and the NMOS transistor 110, and the state in which the overcurrent is passed is rapidly changed to the state in which the current is not passed at the output terminal 114 as illustrated in FIG. 10C. As a result, a surge current is generated at the output terminal 114, the output voltage of the amplifier 100 temporarily becomes lower than the ground voltage due to the generated surge current as illustrated in FIG. 10A, and therefore, the latch-up is generated in the PMOS transistor 106 and the NMOS transistor 110 to break down the PMOS transistor 106 and the NMOS transistor 110.